Most advanced exposure tools employ an ASML scanner, which requires a SPM to align a current layer to a previous layer in the fabrication of semiconductor devices. Traditional methods use an RX pad to reduce noise from a previous layer when using SPM alignment marks to align the current layer with the previous layer. However, traditional methods require a large RX pad size, for instance, a 40 micron (μm) by 436.6 μm pad for a narrow short-scribe-lane primary mark in order to effectively reduce noise between layers. As such, traditional methods using a SPM and RX pad exceed design rules checks for maximum pad size, for instance, 50 μm by 50 μm, and cause non-uniformity of chemical-mechanical planarization (CMP) processes for the IC. Furthermore, as feature sizes continue to decrease, so increases the importance of uniformity of CMP processes for the IC. Some traditional methods attempt to solve the CMP non-uniformity issues by using a large shallow trench isolation (STI) pad. However, the large STI pad causes a dishing of polish oxide, and is thus ineffective.
A need therefore exists for an RX pad for use with gate alignment marks configured to enable sufficient filtering of noise between layers while resulting in little or no non-uniformity of CMP processes for the IC.